View Z16C3010VSC_878280.PDF datasheet online --- IC-ON-LINE

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PRODUCT SPECIFICATION
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Two Independent 0-to-10-mbps Full-Duplex Channels, each with Two Baud Rate Generators and One Digital Phase-Locked Loop for Clock Recovery 32-Byte Data FIFO's for each Receiver and Transmitter 110-ns Bus Cycle Time, 16-Bit Data Bus Bandwidth Multi-Protocol Operation under Program Control with Independent Mode Selection for Receiver and Transmitter Async Mode with 1 to 8 Bits/Character, 1/16 to 2 Stop Bits/Character in 1/16-Bit Increments; Programmable Clock Factor; Break Detect and Generation; Odd, Even, Mark, Space or no Parity and Framing Error Detection; Supports One Address/Data Bit and MIL STD 1553B Protocols Byte Oriented Synchronous Mode with One to Eight Bits/Character; Programmable Idle Line Condition; Optional Receive Sync Stripping; Optional Preamble Transmission; 16- or 32-Bit CRC and Transmit-to-Receive Slaving (for X.21) Bisync Mode with 2- to 16-Bit Programmable Sync Character; Programmable Idle Line Condition; Optional
Receive Sync Stripping; Optional Preamble Transmission; 16- or 32-Bit CRC
*
Transparent Bisync Mode with EBCDIC or ASCII Character Code; Automatic CRC Handling; Programmable Idle Line Condition; Optional Preamble Transmission; Automatic Recognition of DLE, SYN, SOH, ITX, ETX, ETB, EOT, ENQ and ITB External Character Sync Mode for Receive HDLC/SDLC Mode with Eight-Bit Address Compare; Extended Address Field Option; 16- or 32-Bit CRC; Programmable Idle Line Condition; Optional Preamble Transmission and Loop Mode DMA Interface with Separate Request and Acknowledge for Each Receiver and Transmitter Channel Load Command for DMA Controlled Initialization Flexible Bus Interface for Direct Connection to Most Microprocessors; User Programmable for 8 or 16 Bits Wide. Directly Supports 680X0 Family or 8X86 Family Bus Interfaces Low Power CMOS 68-Pin PLCC/100-Pin VQFP Packages
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The Z16C30 USCTM Universal Serial Controller is a dualchannel multi-protocol data communications peripheral designed for use with any conventional multiplexed or nonmultiplexed bus. The USC functions as a serial-to-parallel, parallel-to-serial converter/controller and may be software configured to satisfy a wide variety of serial communications applications. The device contains a variety of new, sophisticated internal functions including two baud rate generators per channel, one digital phase-locked loop per
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channel, character counters for both receive and transmit in each channel and 32-byte data FIFO's for each receiver and transmitter (Figure 1). ZiLOG now offers a high speed version of the USC with improved bus bandwidth. CPU bus accesses have been shortened from 160 ns per access to 110 ns per access. The USC has a transmit and receive clock range of up to 10 MHz
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(20 MHz when using the DPLL, BRG, or CTR) and data transfer rates as high as 10 Mbits/sec full duplex. The USC handles asynchronous formats, synchronous byte-oriented formats such as BISYNC and synchronous bit-oriented formats such as HDLC. This device supports virtually any serial data transfer application. The device can generate and check CRC in any synchronous mode and can be programmed to check data integrity in various modes. The USC also has facilities for modem controls in both channels. In applications where these controls are not needed, the modem controls may be used for generalpurpose I/O. The same is true for most of the other pins in each channel. Interrupts are supported with a daisy-chain hierarchy, with the two channels having completely separate interrupt structures. High-speed data transfers through DMA are supported by a Request/Acknowledge signal pair for each receiver and transmitter. The device supports automatic status transfer through DMA and also allows device initialization under DMA control.
0QVG When written to, all reserved bits must be programmed to 0.
To aid the designer in efficiently programming the USC, support tools are available. The Technical Manual describes in detail all features presented in this Product Specification and gives programming sequence hints. The Programmer's Assistant is a MS-DOS disk-based programming initialization tool to be used in conjunction with the Technical Manual. There are also available assorted application notes and development boards to assist the designer in the hardware/software development. All Signals with an overline, are active Low. For example: B/W, in which WORD is active Low, and B/W, in which BYTE is active Low. Power connections follow these conventional descriptions:
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PIN DESCRIPTION
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TXACKA WAIT/4&; SITACK A/$ D/% CS RESET VCC VCC VCC AS DS RD WR R/9 PITACK TXACKB 60
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TXREQA RXCA RXDA DCDA TXCA TXDA CTSA GND GND GND CTSB TXDB TXCB DCDB RXDB RXCB TXREQB
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The Z16C30 contains 13 pins per channel for channel I/O, 16 pins for address and data, 12 pins for CPU handshake and 14 pins for power and ground. Three separate bus interface types are available for the device. The Bus Configuration Register (BCR) and external connections to the AD bus control selection of the bus type. A 16-bit bus is selected by setting BCR bit 2 to a 1. The 8bit bus is selected by setting BCR bit 2 to 0 and tying AD15-AD8 to VSS.
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The 8-bit bus with separate address is selected by setting BCR bit 2 to 0 and, during the BCR write, forcing AD15 to a 1 and forcing AD14-AD8 to 0. The multiplexed bus is selected for the USC if there is an Address Strobe prior to or during the transaction which writes the BCR. If no Address Strobe is present prior to or during the transaction which writes the BCR, a nonmultiplexed bus is selected (see Figure 29).
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KPRWV CEVKXG .QY This signal resets the device to a known state. The first write to the USC after a reset accesses the BCR to select additional bus options for the device. #5 #FFTGUU 5VTQDG
KPRWV CEVKXG .QY This signal is used in the multiplexed bus modes to latch the address on the AD lines. The AS signal is not used in the nonmultiplexed bus modes and should be tied to VDD. &5 &CVC 5VTQDG
KPRWV CEVKXG .QY This signal strobes data out of the device during a read and may strobe an interrupt vector out of the device during an interrupt acknowledge cycle. DS also strobes data into the device on the state of R/W. 4& 4GCF 5VTQDG
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KPRWV CEVKXG .QY This signal is a strobe signal that indicates that an in-
terrupt acknowledge cycle is in progress. The device is capable of returning an interrupt vector that may be encoded with the type of interrupt pending during this acknowledge cycle. PITACK may be programmed to accept a single pulse or double pulse acknowledge type. This programming is done in the BCR. With the double pulse type selected, the first PITACK is recognized but no action takes place. The interrupt vector is returned on the second pulse if the no vector option is not selected. The double pulse type is compatible with 8X86 family microprocessors.
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QWVRWV CEVKXG .QY T h i s signal serves to indicate when the data is available during a read cycle, when the device is ready to receive data during a write cycle, and when a valid vector is available during an interrupt acknowledge cycle. It may be programmed to function either as a Wait signal or a Ready signal using the state of the A/$ pin during the BCR write. When A/B is High during the BCR write, this signal functions as a wait output and thus supports the READY function of 8X86 family microprocessors. When A/B is Low during the BCR write, this signal functions as a ready output and thus supports the DTACK function of 680X0 family microprocessors. #& #& #FFTGUU&CVC $WU
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data out of the device during a read and may strobe an interrupt vector out of the device during an interrupt acknowledge cycle.
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signal
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KPRWV This signal determines the direction of data transfer for a read or write cycle in conjunction with DS. %5 %JKR 5GNGEV
KPRWV CEVKXG .QY This signal selects
the device for access and must be asserted for read and write cycles, but is ignored during interrupt acknowledge and flyby DMA transfers. In the case of a multiplexed bus interface, CS is latched by the rising edge of AS.
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KPRWV This signal selects between the two channels in the device. High selects channel A and Low selects channel B. This signal is sampled and the result is latched during the BCR (Bus Configuration Register) write. It programs the sense of the WAIT/RDY signal appropriate for different bus interfaces. &% &CVC%QPVTQN 5GNGEV
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KPRWV CEVKXG .QY This signal is a status signal that indicates that an in-
data to and from, the device. When the 16-bit nonmultiplexed bus is selected, AD15-AD0 carry data to and from the device. Addresses are provided using a pointer within the device that is loaded with the desired register address. When selecting the 8-bit nonmultiplexed bus (without separate address) only AD7-AD0 are used to transfer data. The pointer is used for addressing, with AD15-AD8 unused. When selecting the 8-bit nonmultiplexed bus (with separate address), AD7-AD0 are used to transfer data with AD15-AD8 used as address bus. When the 16-bit multiplexed bus is selected, addresses are latched from AD7-AD0 and data transfers are sixteen bits wide. When selecting the 8-bit multiplexed bus (without separate address) only AD7-AD0 are used to transfer addresses and data, with AD15-AD8 unused. When the 8-bit multiplexed bus with separate address is selected, only AD7-AD0 are used to transfer data, while AD15-AD8 are used as an address bus.
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QWVRWVU CEVKXG .QY T h e s e signals indicate that the channel has an interrupt condition pending and is requesting service. These outputs are NOT open-drain.
terrupt acknowledge cycle is in progress. The device is capable of returning an interrupt vector that may be encoded with the type of interrupt pending during this acknowledge cycle. This signal is compatible with 680X0 family microprocessors.
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KPRWVU CEVKXG *KIJ T h e IEI signal for each channel is used with the accompanying IEO signal to form an interrupt daisy chain. An active IEI indicates that no device having higher priority is requesting or servicing an interrupt. +'1# +'1$ +PVGTTWRV 'PCDNG 1WV
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as outputs for various transmitter signals or internal clock signals.
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The IEO signal for each channel is used with the accompanying IEI signal to form an interrupt daisy chain. IEO is Low if IEI is Low, an interrupt is under service in the channel, or an interrupt is pending during an interrupt acknowledge cycle.
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functional blocks within the device. They may also be used as outputs for various receiver signals or internal clock signals.
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KPRWVU QT QWVRWVU CEVKXG .QY The primary function of these signals is to re-
nals is to perform fly-by DMA transfers to the transmit FIFOs. They may also be used as bit inputs or outputs.
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KPRWVU QT QWVRWVU CEVKXG .QY The primary function of these sig-
quest DMA transfers from the receive FIFOs. They may also be used as simple inputs or outputs.
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KPRWVU QT QWVRWVU CEVKXG .QY These signals are used as enables for the respective
nals is to perform fly-by DMA transfers from the receive FIFOs. They may also be used as bit inputs or outputs.
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signals carry the serial receive data for each channel.
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spective receivers. They may also be programmed to generate interrupts on either transition or used as simple inputs or outputs.
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Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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The DC Characteristics and Capacitance section below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 5). Standard conditions are as follows:
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CAPACITANCE
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The USC interface timing is similar to that found on a static RAM, except that it is much more flexible. Up to eight separate timing strobe signals may be present on the interface: DS, RD, WR, PITACK, RxACKA, RxACKB, TxACKA and TxACKB. Only one of these timing strobes may be active at any time. Should the external logic activate more than one of these strobes at the same time the USC will enter a pre-reset state that is only exited by a hardware reset. Do not allow overlap of timing strobes. The timing diagrams, beginning on the next page, illustrate the different bus transactions possible, with the necessary setup, hold and delay times.
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The USC internal structure includes two completely independent full-duplex serial channels, each with two baud rate generators, a digital phase-locked loop for clock recovery, transmit and receive character counters and a full-duplex DMA interface. The two serial channels share a common bus interface. The bus interface is designed to provide easy interface to most microprocessors, whether they employ a multiplexed or nonmultiplexed, 8-bit or16-bit bus structure. Each channel is controlled by a set of thirty 16-bit registers, nearly all of which are readable and writable. There is one additional 16-bit register in the bus interface used to configure the nature of the bus interface. The BCR functions are shown in below.
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Both the transmitter and the receiver in the channel are actually microcoded serial processors. As the data shifts through the transmit or receive shift register, the microcode watches for specific bit patterns, counts bits, and at the appropriate time transfers data to or from the FIFOs. The microcode also checks status and generates status interrupts as appropriate.
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The functional capabilities of the USC are described from two different points of view: as a data communications device, it transmits and receives data in a wide variety of data communications protocols; as a microprocessor peripheral, the USC offers such features as read/write registers, a flexible bus interface, DMA interface support and vectored interrupts. ly independent, as are the two channels. Each receiver and transmitter is supported by a 32-byte deep FIFO and a 16bit message length counter. All modes allow optional even, odd, mark or space parity. Synchronous modes allow the choice of two 16-bit or one 32-bit CRC polynomial. Selection of from one to eight bits-per-character is available in both receiver and transmitter, independently. Error and status conditions are carried with the data in the receive and transmit FIFOs to greatly reduce the CPU overhead required to send or receive a message. Specific, appropriately timed interrupts are available to signal such conditions as overrun, parity error, framing error, end-of-frame, idle line received, sync acquired, transmit underrun, CRC sent, clos&55%%
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The USC provides two independent full-duplex channels programmable for use in any common data communication protocol. The receiver and transmitter modes are complete
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<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT $KU[PE 6TCPURCTGPV /QFG In this mode, the synchronization pattern is DLE-SYN, programmable selected from either ASCII or EBCDIC encoding. The receiver recognizes control character sequences and automatically handles CRC calculation without CPU intervention. The transmitter can be programmed to send either SYN, DLE-SYN, CRC-SYN, or CRC-DLE-SYN upon underrun and can automatically send the closing DLE-SYN with optional CRC at the end of a programmed message length. 0$+2 /QFG This mode is identical to async except that the receiver checks for the status of an additional address/data bit between the parity bit and the stop bit. The value of this bit is FIFO'ed along with the data. This bit is automatically inserted in the transmitter with the value that is FIFO'ed with the transmit data. /QFG This mode implements the data format of IEEE 802.3 with 16-bit address compare. In this mode, DCD and CTS are used to implement the carrier sense and collision detect interactions with the receiver and transmitter. 5NCXGF /QPQU[PE /QFG This mode is available only in
ing sync/flag sent, abort sent, idle line sent and preamble sent. In addition, several useful internal signals such as receive FIFO load, received sync, transmit FIFO read and transmission complete may be sent to pins for use by external circuitry.
#U[PEJTQPQWU /QFG The receiver and transmitter can handle data at a rate of 1/16, 1/32, or 1/64 the clock rate. The receiver rejects start bits less than one-half a bit time and will not erroneously assemble characters following a framing error. The transmitter is capable of sending one, two, or anywhere in the range of 1/16 to two stop bits per character in 1/16 bit increments. 'ZVGTPCN 5[PE /QFG The receiver is synchronized to the receive data stream by an externally-supplied signal on a pin for custom protocol applications. +UQEJTQPQWU /QFG Both transmitter and receiver may op-
erate on start-stop (async) data using a 1x clock. The transmitter can send one or two stop bits.
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Isochronous mode except that the start bit is replaced by a three bit-time code violation pattern as in MIL-STD 1553B. The transmitter can send zero, one or two stop bits.
/QPQU[PE /QFG In this mode, a single character is used for synchronization. The sync character can be either eight bits long with an arbitrary data character length, or programmed to match the data character length. The receiver is capable of automatically stripping sync characters from the received data stream. The transmitter may be programmed to automatically send CRC on either an underrun or at the end of a programmed message length. $KU[PE /QFG This mode is identical to monosync mode except that character synchronization requires two successive characters for synchronization. The two characters need not be identical. *&.% /QFG In this mode, the receiver recognizes flags, performs optional address matching, accommodates extended address fields, 8- or 16-bit control fields and logical control fields, performs zero deletion and CRC checking. The receiver is capable of receiving shared-zero flags, recognizes the abort sequence and can receive arbitrary length messages. The transmitter automatically sends opening and closing flags, performs zero insertion and can be programmed to send an abort, an extended abort, a flag or CRC and a flag on transmit underrun. The transmitter can also automatically send the closing flag with optional CRC at the end of a programmed message length. Shared-zero flags are selected in the transmitter and a separate character length may be programmed for the last character in the frame. &55%%
the transmitter and allows the transmitter (operating as though it were in monosync mode) to send data that is bytesynchronous to the data being received by the receiver.
*&.% .QQR /QFG This mode is also available only in the transmitter and allows the USC to be used in an HDLC loop configuration. In this mode, the receiver is programmed to operate in HDLC mode so that the transmitter echoes received messages. Upon receipt of a particular bit pattern (actually a sequence of seven consecutive ones) the transmitter breaks the loop and inserts its own frame(s).
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The USC may be programmed to encode and decode the serial data in any of eight different ways as shown in Figure 28. The transmitter encoding method is selected independently of the receiver decoding method.
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04<$ Data is inverted from NRZ. 04<+/CTM In NRZI-Mark, a 1 is represented by a transition at the beginning of the bit cell. That is, the level present in the preceding bit cell is reversed. A 0 is represented by the absence of a transition at the beginning of the bit cell. 04<+5RCEG In NRZI-Space, a 1 is represented by the absence of a transition at the beginning of the bit cell. That is, the level present in the preceding bit cell is maintained. A
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0 is represented by a transition at the beginning of the bit cell.
$KRJCUG/CTM In Biphase-Mark, a 1 is represented by a transition at the beginning of the bit cell and another transition at the center of the bit cell. A 0 is represented by a transition at the beginning of the bit cell only. $KRJCUG5RCEG In Biphase-Space, a 1 is represented by a transition at the beginning of the bit cell only. A 0 is repre-
sented by a transition at the beginning of the bit cell and another transition at the center of the bit cell.
$KRJCUG.GXGN In Biphase-Level, a 1 is represented by a High during the first half of the bit cell and a Low during the second half of the bit cell. A 0 is represented by a Low during the first half of the bit cell and a High during the second half of the bit cell.
Data NRZ
1
1
0
0
1
0
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Each channel in the USC contains a 16-bit character counter for both receiver and transmitter. The receive character counter may be preset either under software control or automatically at the beginning of a receive message. The counter decrements with each receive character and at the end of the receive message the current value in the counter is automatically loaded into a four-deep FIFO. This allows DMA transfer of data to proceed without CPU intervention at the end of a received message, as the values in the FIFO
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allow the CPU to determine message boundaries in memory. Similarly, the transmit character counter is loaded either under software control or automatically at the beginning of a transmit message. The counter is decremented with each write to the transmit FIFO. When the counter has decremented to 0, and that byte is sent, the transmitter automatically terminates the message in the appropriate fashion (usually CRC and the closing flag or sync character) without requiring CPU intervention.
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Each channel in the USC contains two baud rate generators. Each generator consists of a 16-bit time constant register and a 16-bit down counter. In operation, the counter decrements with each baud rate generator clock, with the time constant automatically reloaded when the count reaches zero. The output of the baud rate generator toggles when the counter reaches a count of one-half of the time constant and again when the counter reaches zero.A new time constant may be written at any time but the new value will not take effect until the next load of the counter. The outputs of both baud rate generators are sent to the clock multiplexer for use internally or externally. The baud rate generator output frequency is related to the baud rate generator input clock frequency by the following formula: Output frequency = Input frequency/(time constant + 1). This allows an output frequency in the range of 1 to 1/65536 of the input frequency, inclusive.
data rate. The DPLL uses this clock, along the data stream, to construct a clock for the data. This clock may then be routed to the receiver, transmitter, or both, or to a pin for use externally. In all modes, the DPLL counts the input clock to create nominal bit times. As the clock is counted, the DPLL watches the incoming data stream for transitions. Whenever a transition is detected, the DPLL makes a count adjustment (during the next counting cycle), to produce an output clock which tracks the incoming bit cells. The DPLL provides properly phased transmit and receive clocks to the clock multiplexer.
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Each channel contains two 5-bit counters, which are programmed to divide an input clock by 4, 8, 16 or 32. The inputs of these two counters are sent to the clock multiplexer. The counters are used as prescalers for the baud rate generators, or to provide a stable transmit clock from a common source when the DPLL is providing the receive clock.
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The clock multiplexer in each channel selects the clock source for the various blocks in the channel and selects an internal clock signal to potentially be sent to either the RxC or TxC pin.
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The USC can be programmed for local loopback or auto echo operation. In local loopback, the output of the transmitter is internally routed to the input of the receiver. This allows testing of the USC data paths without any external logic. Auto echo connects the RxD pin directly to the TxD pin. This is useful for testing serial links external to the USC.
&KIKVCN 2JCUG.QEMGF .QQR
Each channel in the USC contains a Digital Phase-Locked Loop (DPLL) to recover clock information from a data stream with NRZI or Biphase encoding. The DPLL is driven by a clock that is nominally 8, 16 or 32 times the receive
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
+1 +06'4(#%' %#2#$+.+6+'5
The USC offers the choice of polling, interrupt (vectored or nonvectored) and block transfer modes to transfer data, status and control information to and from the CPU. knowledge cycle if there are no higher priority devices requesting interrupts. There are six sources of interrupt in each channel: Receive Status, Receive Data, Transmit Status, Transmit Data, I/O Status and Device Status, prioritized in that order within the channel. There are six sources of Receive Status interrupt, each individually enabled: exited hunt, idle line, break/abort, code violation/end-of-transmission/end-offrame, parity error and overrun error. The Receive Data interrupt is generated whenever the receive FIFO fills with data beyond the level programmed in the Receive Interrupt Control Register (RICR). There are six sources of Transmit Status interrupt, each individually enabled: preamble sent, idle line sent, abort sent, end-of-frame/end-of-transmission sent, CRC sent and underrun error. The Transmit Data interrupt is generated whenever the transmit FIFO empties below the level programmed in the Transmit Interrupt Control Register (TICR). The I/O Status interrupt serves to report transitions on any of six pins. Interrupts are generated on either or both edges with separate selection and enables for each pin. The pins programmed to generate I/O Status interrupts are RxC, TxC, RxREQ, TxREQ, DCD and CTS. These interrupts are independent of the programmed function of the pins. The Device Status interrupt has four separately enabled sources: receive character count FIFO overflow, DPLL sync acquired, BRG1 zero count and BRGO zero count.
2QNNKPI
All interrupts are disabled. The registers in the USC are automatically updated to reflect current status. The CPU polls the Daisy Chain Control Register (DCCR) to determine status changes and then reads the appropriate status register to find and respond to the change in status. USC status bits are grouped according to function to simplify this software action.
+PVGTTWRV
When a USC responds to an interrupt acknowledge from the CPU, an interrupt vector may be placed on the data bus. This vector is held in the Interrupt Vector Register (IVR). To speed interrupt response time, the USC modifies three bits in this vector to indicate which type of interrupt is being requested. Each of the six sources of interrupts in each channel of the USC (Receive Status, Receive Data, Transmit Status, Transmit Data, I/O Status and Device Status) has three bits associated with the interrupt source: Interrupt Pending (IP), Interrupt-Under-Service (IUS) and Interrupt Enable (IE). If the IE bit for a given source is set, that source can request interrupts. Note that individual sources within the six groups also have interrupt enable bits which are set for the particular source. In addition, there is a Master Interrupt Enable (MIE) bit in each channel which globally enables or disables interrupts within the channel. The other two bits are related to the interrupt priority chain. A channel in the USC may request an interrupt only when no higher priority interrupt source is requesting one, e.g., when IEI is High for the channel. In this case the channel activates the INT signal. The CPU then responds with an interrupt acknowledge cycle, and the interrupting channel places a vector on the data bus. In the USC, the IP bit signals that an interrupt request is being serviced. If an IUS is set, all interrupt sources of lower priority within the channel and external to the channel are prevented from requesting interrupts. The internal interrupt sources are inhibited by the state of the internal daisy chain, while lower priority devices are inhibited by the IEO output of the channel being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an interrupt ac-
$NQEM 6TCPUHGT /QFG
The USC accommodates block transfers through DMA through the RxREQ, TxREQ, RxACK and TxACK pins. The RxREQ signal is activated when the fill level of the receive FIFO exceeds the value programmed in the RICR. The DMA may respond with either a normal bus transaction or by activating the RxACK pin to read the data directly (flyby transfer). The TxREQ signal is activated when the empty level of the transmit FIFO falls below the value programmed in the TICR. The DMA may respond either with a normal bus transaction or by activating the TxACK pin to write the data directly (fly-by transfer). The RxACK and TxACK pin functions for this mode are controlled by the Hardware Configuration Register (HCR). Then using the RxACK and TxACK pins to transfer data, no chip select is necessary; these are dedicated strobes for the appropriate FIFO.
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
241)4#//+0)
The registers in each USC channel are programmed by the system to configure the channels. Before this can occur, however, the system must program the bus interface by writing to the Bus Configuration Register (BCR). The BCR has no specific address and is only accessible immediately after a hardware reset of the device. The first write to the USC, after a hardware reset, programs the BCR. From that time on, the normal channel registers may be accessed. No specific address need be presented to the USC for the BCR write because the first write after a hardware reset is automatically programmed for the BCR. In the multiplexed bus case, all registers are directly addressable through the address latched by AS at the beginning of a bus transaction. The address is decoded from either AD6-AD0 or AD7-AD1. This is controlled by the Shift Right/Shift Left bit in the BCR. The address maps for these two cases are shown in Table 2. The D/C pin is still used to directly access the receive and transmit data registers (RDR and TDR) in the multiplexed bus; if D/C is High the address latched by AS is ignored and an access of RDR or TDR is performed. In the nonmultiplexed bus case, the registers in each channel are accessed indirectly using the address pointer in the Channel Command/Address Register (CCAR) in each channel. The address of the desired register is first written to the CCAR and then the selected register is accessed; the pointer in the CCAR is automatically cleared after this access. The RDR and TDR are accessed directly using the D/C pin, without disturbing the contents of the pointer in the CCAR.
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There are two important things to note about the USC. First, the Channel Reset bit in the CCAR places the channel in the reset state. To exit this reset state either a word of all zeros must be written to the CCAR (16-bit bus) or a byte of all zeros must be written to the lower byte of the CCAR (8-bit bus). The second thing to note is that after reset, the transmit and receive clocks are not connected. The first thing that should be done in any initialization sequence is a write to the Clock Mode Control Register (CMCR) to select a clock source for the receiver and transmitter. The register addressing is shown in Table 3 while the bit assignments for the registers are shown in Figure 29.
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
Rqq 5A ggiu T UAT AgpACixpus 67RAWuq HA5S 5AFqgAIqA5S
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&55%%
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&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
%10641. 4')+56'45
#FFTGUU & & & & & & & & & & & & & & & & 7RRGT.QYGT $[VG 5GNGEV
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&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &

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&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & &

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: &CVC 4CVG : &CVC 4CVG : &CVC 4CVG 4GUGTXGF
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: &CVC 4CVG : &CVC 4CVG : &CVC 4CVG 4GUGTXGF
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#FFTGUU & & & & & & & & & & & & & & & &

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&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
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#FFTGUU & & & & & & & & & & & & & & & &
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/+. 56&
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & &

/QPQU[PE
4GEGKXGT /QFG
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/QPQU[PE
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&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
$KU[PE
4GEGKXGT /QFG 4Z 5JQTV 5[PE %JCTCEVGT 4Z 5[PE 5VTKR 4GUGTXGF

$KU[PE
6TCPUOKVVGT /QFG 6Z 5JQTV 5[PE %JCTCEVGT 6Z 2TGCODNG 'PCDNG

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&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & &

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4GEGKXGT /QFG

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&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
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&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & &

0$+2
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: &CVC 4CVG : &CVC 4CVG : &CVC 4CVG 4GUGTXGF 4Z 2CTKV[ QP &CVC 4GUGTXGF

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: &CVC 4CVG : &CVC 4CVG : &CVC 4CVG 4GUGTXGF
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&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &

4GEGKXGT /QFG 4Z #FFTGUU 5GCTEJ 4GUGTXGF

6TCPUOKVVGT /QFG 4GUGTXGF 6Z %4% QP 7PFGTTWP
(KIWTG %JCPPGN /QFG 4GIKUVGT /QFG
#FFTGUU & & & & & & & & & & & & & & & &
4GUGTXGF 4GUGTXGF
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5NCXGF /QPQU[PE
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&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
ZiLOG

4GUGTXGF
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#DQTV 'ZVGPFGF #DQTV (NCI %4%(NCI
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&55%%
ZiLOG
#FFTGUU & & & & & & & & & & & & & & &
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&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & & 4GUGTXGF
ZiLOG
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0Q 5VCVWU $NQEM 1PG 9QTF 5VCVWU $NQEM 6YQ 9QTF 5VCVWU $NQEM 4GUGTXGF
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#FFTGUU & & & & & & & & & & & & & & & &
4GUGTXGF
(KIWTG 2TKOCT[ 4GUGTXGF 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
4GUGTXGF
(KIWTG 5GEQPFCT[ 4GUGTXGF 4GIKUVGT
#FFTGUU & & & & & & & & & & & & & & & & 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC 6GUV &CVC
(KIWTG 6GUV /QFG &CVC 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
ZiLOG

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4GUGTXGF
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&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &

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&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
ZiLOG
$4) 'PCDNG $4) 5KPING %[ENG%QPVKPWQWU 5VCVG 1WVRWV 4Z #EMPQYNGFIG +PRWV 1WVRWV 1WVRWV $4) 'PCDNG $4) UKPING %[ENGEQPVKPWQWU 5VCVG 1WVRWV 6Z #EMPQYNGFIG +PRWV 1WVRWV 1WVRWV
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%64 %NQEM 4CVG
(KIWTG *CTFYCTG %QPHKIWTCVKQP 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
+8 +8 +8 +8 +8 +8 +8 +8 +8
4

0QPG &GXKEG 5VCVWU +1 5VCVWU 6TCPUOKV &CVC 6TCPUOKV 5VCVWU 4GEGKXG &CVC 4GEGKXG 5VCVWU 0QV 7UGF
/QFKHKGF 8GEVQT
4
+8
4 +8
4 +8
4 +8
4
(KIWTG +PVGTTWRV 8GEVQT 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & &

+PRWV 2KP 4Z %NQEM 1WVRWV 4Z $[VG %NQEM 1WVRWV 5;0% 1WVRWV $4) 1WVRWV $4) 1WVRWV %64 1WVRWV &2.. 4Z 1WVRWV
4Z% 2KP %QPVTQN
+PRWV 2KP 6Z ENQEM 1WVRWV 6Z $[VG ENQEM 1WVRWV 6Z %QORNGVG 1WVRWV $4) 1WVRWV $4) 1WVRWV %64 1WVRWV &2.. 1WVRWV
6Z% 2KP %QPVTQN
6Z &CVC 1WVRWV 5VCVG 1WVRWV 1WVRWV 1WVRWV
6Z& 2KP %QPVTQN
5VCVG 1WVRWV 4Z 4GSWGUV 1WVRWV 1WVRWV 1WVRWV
4Z4'3 2KP %QPVTQN
5VCVG 1WVRWV 6Z 4GSWGUV 1WVRWV 1WVRWV 1WVRWV &%& 2KP %QPVTQN
6Z4'3 2KP %QPVTQN
&%& +PRWV &%&5;0% +PRWV 1WVRWV 1WVRWV
%65 +PRWV %65 +PRWV 1WVRWV 1WVRWV
%65 2KP %QPVTQN
(KIWTG +1 %QPVTQN 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
&GXKEG 5VCVWU +' +1 5VCVWU +' 6TCPUOKV &CVC +' 6TCPUOKV 5VCVWU +' 4GEGKXG &CVC +' 4GEGKXG 5VCVWU +' 0WNN EQOOCPF 0WNN EQOOCPF 4GUGV +' 5GV +'
+' %QOOCPF
9 4GEGKXGF

#NN #NN +1 5VCVWU CPF #DQXG 6TCPUOKV &CVC CPF #DQXG 6TCPUOKV 5VCVWU CPF #DQXG 4GEGKXG &CVC 4GEGKXG 5VCVWU 1PN[ 0QPG
8+5 .GXGN
8+5 08 &.% /+'
(KIWTG +PVGTTWRV %QPVTQN 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & &
&GXKEG 5VCVWU +2 +1 5VCVWU +2 6TCPUOKV &CVC +2 6TCPUOKV 5VCVWU +2 4GEGKXG &CVC +2 4GEGKXG 5VCVWU +2 0WNN EQOOCPF 4GUGV +2 CPF +75 4GUGV +2 5GV +2
+2 %QOOCPF
9 &GXKEG 5VCVWU +75 +1 5VCVWU +75 6TCPUOKV &CVC +75 6TCPUOKV 5VCVWU +75 4GEGKXG &CVC +75 4GEGKXG 5VCVWU +75

0WNN EQOOCPF 0WNN EQOOCPF 4GUGV +75 5GV +75
+75 %QOOCPF
9
(KIWTG &CKU[%JCKP %QPVTQN 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & & $4) <% .CVEJGF7PNCVEJ $4) <% NCVEJGF7PNCVEJ &2.. 5;0% NCVEJGF7PNCVEJ 4%% 1XGTHNQY .CVEJGF7PNCVEJ %65
4 %65 .CVEJGF7PNCVEJ &%&
4 &%& .CVEJGF7PNCVEJ 6Z4'3
4 6Z4'3 .CVEJGF7PNCVEJ 4Z4'3
4 4Z4'3 .CVEJGF7PNCVEJ 6Z%
4 6Z% .CVEJGF7PNCVEJ 4Z%
4 4Z% .CVEJGF7PNCVEJ
(KIWTG /KUEGNNCPGQWU +PVGTTWRV 5VCVWU 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
ZiLOG
$4) <% +' $4) <% +' &2.. 5;0% +' 4%% 1XGTHNQY +' &KUCDNGF 4KUKPI 'FIG 1PN[ (CNNKPI 'FIG 1PN[ $QVJ 'FIGU
%65 +PVGTTWRVU

&KUCDNGF 4KUKPI 'FIG 1PN[ (CNNKPI 'FIG 1PN[ $QVJ 'FIGU
&%& +PVGTTWRVU
&KUCDNGF 4KUKPI 'FIG 1PN[ (CNNKPI 'FIG 1PN[ $QVJ 'FIGU
6Z4'3 +PVGTTWRVU
&KUCDNGF 4KUKPI 'FIG 1PN[ (CNNKPI 'FIG 1PN[ $QVJ 'FIGU
4Z4'3 +PVGTTWRVU
&KUCDNGF 4KUKPI 'FIG 1PN[ (CNNKPI 'FIG 1PN[ $QVJ 'FIGU
6Z% +PVGTTWRVU
&KUCDNGF 4KUKPI 'FIG 1PN[ (CNNKPI 'FIG 1PN[ $QVJ 'FIGU
4Z% +PVGTTWRVU
(KIWTG 5VCVWU +PVGTTWRV %QPVTQN 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU Z & & & & & & & & & & & & & & & &
4Z 4Z 4Z 4Z 4Z
4
4
4
4
4
4Z
4 4Z 4Z
4
4
4Z
4 4Z 4Z 4Z 4Z 4Z 4Z 4Z
4
4
4
4
4
4
4
(KIWTG 4GEGKXG &CVC 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
ZiLOG
$KVU $KV $KVU $KVU $KVU $KVU $KVU $KVU

&KUCDNG +OOGFKCVGN[ &KUCDNG #HVGT 4GEGRVKQP 'PCDNG 9KVJQWV #WVQ'PCDNGU 'PCDNG 9KVJ #WVQ'PCDNG
4Z 'PCDNG
4Z %JCTCEVGT .GPIVJ

'XGP 1FF 5RCEG /CTM
4Z 2CTKV[ 5GPUG 3WGWG #DQTV 4Z %4% 'PCDNG 4Z %4% 2TGUGV 8CNWG

%4%%%+66 %4% %4% 4GUGTXGF
4Z %4% 2QN[PQOKCN
04< 04<$ 04<+/CTM 04<+5RCEG $KRJCUG/CTM $KRJCUG5RCEG $KRJCUG.GXGN &KHH $KRJCUG.GXGN
4Z &CVC &GEQFKPI
(KIWTG 4GEGKXG /QFG 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & & 4Z %JCTCEVGT #XCKNCDNG
4 4Z 1XGTTWP 2CTKV[ 'TTQT(TCOG #DQTV %4%(TCOKPI 'TTQT 4Z %8'16'1( 4Z $TGCM#DQTV 4Z +FNG 'ZKVGF *WPV 5JQTV (TCOG%8 2QNCTKV[
4 4GUKFWG %QFG
4 4GUKFWG %QFG
4 4GUKFWG %QFG
4

0WNN %QOOCPF 4GUGTXGF 2TGUGV %4% 'PVGT *WPV /QFG 4GUGTXGF 5GNGEV (+(1 5VCVWU 5GNGEV (+(1 +PVGTTWRV .GXGN 5GNGEV (+(1 5VCVWU .GXGN 4GUGTXGF 4GUGTXGF 4GUGTXGF 4GUGTXGF 4GUGTXGF 4GUGTXGF 4GUGTXGF 4GUGTXGF
4GEGKXG %QOOCPF
4
(KTUV $[VG KP 'TTQT
4 5GEQPF $[VG KP 'TTQT
4
(KIWTG 4GEGKXG %QOOCPF 5VCVWU 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & & 6%4 4GCF %QWPV6% 4Z 1XGTTWP +# 2CTKV[ 'TTQT(TCOG #DQTV +# 5VCVWU QP 9QTFU 4Z %8'16'1( +# 4Z $TGCM#DQTV +# 4Z +FNG +# 'ZKVGF *WPV +# 4Z (+(1 %QPVTQN CPF 5VCVWU
(KNN+PVGTTWRV&/# .GXGN
(KIWTG 4GEGKXG +PVGTTWRV %QPVTQN 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & & 45;0 45;0 45;0 45;0 45;0 45;0 45;0 45;0 45;0 45;0 45;0 45;0 45;0 45;0 45;0 45;0
(KIWTG 4GEGKXG 5[PE 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & & 4%. 4%. 4%. 4%. 4%. 4%. 4%. 4%. 4%. 4%. 4%. 4%. 4%. 4%. 4%. 4%.
(KIWTG 4GEGKXG %QWPV .KOKV 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
4%% 4%% 4%% 4%% 4%%
4
4
4
4
4
4%%
4 4%% 4%%
4
4
4%%
4 4%% 4%% 4%% 4%% 4%% 4%% 4%%
4
4
4
4
4
4
4
(KIWTG 4GEGKXG %JCTCEVGT %QWPV 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & & 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6%
(KIWTG 6KOG %QPUVCPV 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU Z & & & & & & & & & & & & & & & &
6Z 6Z 6Z 6Z 6Z
9
9
9
9
9
6Z
9 6Z 6Z
9
9
6Z
9 6Z 6Z 6Z 6Z 6Z 6Z
9
9
9
9
9
9
6Z
9
(KIWTG 6TCPUOKV &CVC 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & &
$KVU $KV $KVU $KVU $KVU $KVU $KVU $KVU

&KUCDNG +OOGFKCVGN[ &KUCDNG #HVGT 4GEGRVKQP 'PCDNG 9KVJQWV #WVQ'PCDNGU 'PCDNG 9KVJ #WVQ'PCDNG
6Z 'PCDNG
4Z %JCTCEVGT .GPIVJ
6Z 2CTKV[ GPCDNG 'XGP 1FF 5RCEG /CTM
6Z 2CTKV[ 5GPUG 6Z %4% QP '1('1/ 6Z %4% 'PCDNG 6Z %4% 2TGUGV 8CNWG

%4%%%+66 %4% %4% 4GUGTXGF
6Z %4% 2QN[PQOKCN
04< 04<$ 04<+/CTM 04<+5RCEG $KRJCUG/CTM $KRJCUG5RCEG $KRJCUG.GXGN &KHH $KRJCUG.GXGN
6Z &CVC &GEQFKPI
(KIWTG 6TCPUOKV /QFG 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & & 6Z $WHHGT 'ORV[
4 6Z 7PFGTTWP #NN 5GPV
4 6Z %4% 5GPV 6Z '1('16 5GPV 6Z #DQTV 5GPV 6Z +FNG 5GPV 6Z 2TGCODNG 5GPV 0WNN %QOOCPF 4GUGTXGF 2TGUGV %4% 'PVGT *WPV /QFG 4GUGTXGF 5GNGEV (+(1 5VCVWU 5GNGEV (+(1 +PVGTTWRV .GXGN 5GNGEV (+(1 5VCVWU .GXGN
6Z +FNG .KPG %QPFKVKQP
6Z 9CKV QP 7PFGTTWP 0WNN %QOOCPF 4GUGTXGF 2TGUGV %4% 'PVGT *WPV /QFG 4GUGTXGF 5GNGEV (+(1 5VCVWU 5GNGEV (+(1 +PVGTTWRV .GXGN 5GNGEV (+(1 5VCVWU .GXGN
5GPF (TCOG /GUUCIG 5GPF #DQTV 4GUGTXGF 4GUGTXGF 4GUGV &.' +PJKDKV 5GV &.' +PJKDKV 4GUGV '1('1/ 5GV '16'1/
6TCPUOKV %QOOCPF
9
(KIWTG 6TCPUOKV %QOOCPF5VCVWU 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & & 6%4 4GCF %QWPV6% 6Z 1XGTTWP +# 9CKV HQT 5GPF %QOOCPF 6Z %4% 5GPV +# 6Z '1('16 5GPV +# 6Z #DQTV 5GPV +# 6Z +FNG 5GPV +# 6Z 2TGCODNG 5GPV +# 6Z (+(1 %QPVTQN CPF 5VCVWU
(KNN+PVGTTWRV&/# NGXGN
(KIWTG 6TCPUOKV +PVGTTWRV %QPVTQN 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
65;0 65;0 65;0 65;0 65;0 65;0 65;0 65;0 65;0 65;0 65;0 65;0 65;0 65;0 65;0 65;0
(KIWTG 6TCPUOKV 5[PE 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & & 6%. 6%. 6%. 6%. 6%. 6%. 6%. 6%. 6%. 6%. 6%. 6%. 6%. 6%. 6%. 6%.
(KIWTG 6TCPUOKV %QWPV .KOKV 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU & & & & & & & & & & & & & & & &
6%% 6%% 6%% 6%% 6%% 6%% 6%% 6%% 6%% 6%% 6%% 6%% 6%% 6%% 6%% 6%%
(KIWTG 6TCPUOKV %JCTCEVGT %QWPV 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU & & & & & & & & & & & & & & & & 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6% 6%
(KIWTG 6KOG %QPUVCPV 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
#FFTGUU 0QPG & & & & & & & & & & & & & & & &
4%% 4Z 1XGTTWP 2CTKV[ 'TTQT(TCOG #DQTV %4% 'TTQT 4Z %8'16'1( 4%% (+(1 1XGTHNQY 5JQTV (TCOG%8 2QNCTKV[ 4GUKFWG %QFG 4GUKFWG %QFG 4GUKFWG %QFG (KTUV $[VG KP 'TTQT 5GEQPF $[VG KP 'TTQT 4GHGT VQ (KIWTG %JCPPGN %QPVTQN 4GIKUVGT $KVU HQT #EEGUU /GVJQF
(KIWTG 4GEGKXG 5VCVWU $NQEM 4GIKUVGT
&55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
#FFTGUU 0QPG & & & & & & & & & & & & & & & &
4GUGTXGF $KVU $KV $KVU $KVU $KVU $KVU $KVU $KVU
*&.% 6Z .CUV %JCTCEVGT .GPIVJ
4GUGTXGF 6Z 5WDOQFG 6Z 5WDOQFG 6Z 5WDOQFG 6Z 5WDOQFG 4GHGT VQ (KIWTG %JCPPGN %QPVTQN 4GIKUVGT $KVU HQT #EEGUU /GVJQF
(KIWTG 6TCPUOKV 5VCVWU $NQEM 4GIKUVGT
#FFTGUU 0QPG & & & & & & & & & & & & & & & & 5JKHV 4KIJV #FFTGUUGU &QWDNG2WNUG +06#%$KV $WU 4GUGTXGF 5VCVG #NN 2KPU 5GRCTCVG #FFTGUU HQT $KV $WU /WUV DG RTQITCOOGF CU \GTQ
(KIWTG $WU %QPHKIWTCVKQP 4GIKUVGT
&55%%
ZiLOG
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
2#%-#)' +0(14/#6+10
(KIWTG 2KP 2.%% 2CEMCIG &KCITCO
(KIWTG 2KP 83(2 2CEMCIG &KCITCO &55%%
<% %/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
ZiLOG
14&'4+0) +0(14/#6+10
<%
/*\ 2KP 2.%% <%85%
For fast results, contact your local ZiLOG sales office for assistance in ordering the part desired.
%1&'5
2CEMCIG 6GORGTCVWTG 5RGGF 'PXKTQPOGPVCN 8 2NCUVKE .GCFGF %JKR %CTTKGT 5 u% VQ u% /*\ % 2NCUVKE 5VCPFCTF
'ZCORNG < % 8 5 %
KU C <% /*\ 2.%% VQ % 2NCUVKE 5VCPFCTF (NQY 'PXKTQPOGPVCN (NQY 6GORGTCVWTG 2CEMCIG 5RGGF 2TQFWEV 0WODGT (c)1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE.
Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. ZiLOG, Inc. 910 East Hamilton Avenue, Suite 110 Campbell, CA 95008 Telephone (408) 558-8500 FAX (408) 558-8300 Internet: http://www.zilog.com &55%%

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